1. Field of the Invention
The present invention relates to a method of manufacturing a MIS semiconductor device having an LDD structure wherein at least a portion contacting a channel in a drain region has a relatively low impurity concentration.
2. Description of the Prior Art
A method of manufacturing a MIS semiconductor device having an LDD structure is described in "Monthly Semiconductor World" (1987, February) pp. 94-100 or the like. This method includes steps shown in FIG. 1.
In a prior art in FIG. 1, an SiO.sub.2 film 12 serving as a gate insulating film is formed on an Si substrate 11, and a gate electrode 13 is formed on the SiO.sub.2 film 12. The gate electrode 13 has a polycide structure constituted by a polycrystalline Si film 14 and a WSi.sub.x film 15.
Thereafter, phosphorus ions 16 for forming an n.sup.- -type region for a source/drain region are implanted in the Si substrate 11 using the gate electrode 13 as a mask.
As shown in FIG. 1B, an SiO.sub.2 film 17 is deposited by atmospheric-pressure, low-temperature (about 410.degree. C.) CVD using monosilane or the like. The SiO.sub.2 film 17 is etched by RIE to form side walls of the gate electrode 13 using the SiO.sub.2 film 17.
Thermal oxidation is performed for the resultant structure to respectively form SiO.sub.2 films 21 and 22 on the surfaces of the Si substrate 11 and the WSi.sub.x film 15. Note that the SiO.sub.2 film 21 is used for preventing a decrease in gate breakdown voltage at the edge of the gate electrode 13.
Thereafter, arsenic ions 23 for forming an n.sup.- -type region for a source/drain region are implanted in the Si substrate 11 using the gate electrode 13 and the SiO.sub.2 film 17 as masks.
As shown in FIG. 1C, annealing is performed to the resultant structure to form n.sup.- -type regions 24 and n.sup.+ -type regions 25 serving as source/drain regions.
The thermal oxidation for forming the SiO.sub.2 films 21 and 22 is performed at a temperature within the range of 850.degree. C. to 900.degree. C. In a MIS transistor having a gate length of about 0.8 .mu.m, however, when the high-temperature thermal oxidation is performed for a long time, a junction depth is undesirably increased. Therefore, since the thermal oxidation cannot be sufficiently performed, each of the SiO.sub.2 films 21 and 22 has a thickness of about 100 .ANG..
When the SiO.sub.2 film 21 has such a small thickness, the Si substrate 11 is greatly damaged during ion implantation of the arsenic 23. Therefore, crystal defects easily occur in the Si substrate 11. For this reason, degradation in device characteristics such as an increase in leak current through a junction occurs, and a production yield is decreased.
In addition, since RIE for forming the SiO.sub.2 films 17 serving as the side walls of the gate electrode 13 causes a damage to the surfaces of the Si substrate 11 and the WSi.sub.x film 15, the SiO.sub.2 films 21 and 22 are difficult to grow. For this reason, the thickness of the SiO.sub.2 film 21 is small and, the above problem results in the easy formation of crystal defects in the Si substrate 11 which typically occurs.
Therefore, according to the prior art shown in FIG. 1, a MIS semiconductor device having excellent characteristics cannot be manufactured with a high yield.